USRP N310

The USRP N310 is a networked software defined radio (SDR) that provides reliability and fault-tolerance for deployment in large-scale and distributed wireless systems. The USRP N310 device simplifies control and management of a network of radios by introducing the unique capability to remotely perform tasks such as updating software, rebooting, factory resetting, self-testing, host PC/ARM debugging and monitoring system health.

The USRP N310 is one of the highest channel density devices in the SDR market, offering four RX and four TX channels in a half-wide RU form factor. The RF front end uses two AD9371 transceivers, the latest RFIC technology from Analog Devices. Each channel provides up to 100 MHz of instantaneous bandwidth, and covers an extended frequency range from 10 MHz to 6 GHz.

The open-source USRP Hardware Driver (UHD) API and RF Network-on-Chip (RFNoC) FPGA development framework reduce software development effort and integrate with a variety of industry-standard tools such as GNU Radio. Users can rapidly prototype and reliably deploy designs for a variety of SDR applications such as wireless testbeds, remote radio heads, spectrum monitoring, and more.

Baseband Processor

The baseband processor uses the Xilinx Zynq-7100 SoC to deliver a large user-programmable FPGA for real-time and low-latency processing and a dual-core ARM CPU for stand-alone operation. Users can deploy applications directly on to the preinstalled embedded Linux operating system or stream samples to a host computer using high-speed interfaces such as 1 Gigabit Ethernet, 10 Gigabit Ethernet, and Aurora over two SFP+ ports.

Synchronization

The USRP N310 has a flexible synchronization architecture with support for clock reference, PPS time reference, external LO input, and GPSDO, which enables implementation of high channel count MIMO systems.

Trusted Platform Module (TPM)

The USRP N310 includes a Trusted Platform Module to enable security features such as file encryption and secure boot. Due to product compliance restrictions on products with TPM (Trusted Platform Module) components to a few countries, the USRP N310 is available in two variants:

  • Standard variant with TPM (PN 785067-01)
  • Non-TPM variant (PN 786465-01)

 

Product Photos

N310_Iso.png

USRP N310

USRP N310 Front Panel with 4 RF TX and RX

USRP N310 Front Panel

USRP N310 back panel with digital I/O and Timing

USRP N310 Rear Panel

USRP N310 with entire shipping kit

USRP N310 Shipping Kit

 

USRP N310 Block Diagram

USRP N310 Block Diagram

 

USRP N310 Daughtercard Block Diagram

USRP N310 Daughtercard Block Diagram

[1] The RF front-end uses two AD9371 transceivers that are independently tunable. Each transceiver is capable of 2X2 MIMO operation with LO sharing between each channel.

[2] The RJ45 port is used for remote management of the device and does not support IQ streaming.

[3] The external LO frequency must be twice the center frequency, with center frequency limited to the range from 300 MHz to 4 GHz. Phase coherency is not repeatable after retune or reinitialization of the RF front-end. Phase recalibration is required after these operations. For more information, contact support@ettus.com.

[4] Due to product compliance restrictions on products with TPM (Trusted Platform Module) components to a few countries, the USRP N310 is available in two variants:

  • Standard variant with TPM (PN 785067-01)
  • Non-TPM variant (PN 786465-01)

SKU: 785067-01 Category:

Description

Features

  • High channel density
  • Reliable and fault-tolerant deployment
  • Remote management capability
  • Stand-alone (embedded) or host-based (network streaming) operation
  • Fully integrated and assembled (the USRP N310 does not support swappable daughtercards)
  • 10 MHz to 6 GHz extended frequency range
  • Up to 100 MHz of instantaneous bandwidth per channel
  • 4 RX, 4TX in half-wide RU form factor[1]
  • RX, TX filter bank
  • 16 bit ADC, 14 bit DAC
  • Configurable sample rates: 122.88, 125, and 153.6 MS/s
  • Xilinx Zynq-7100 SoC
    • Dual-core ARM Cortex-A9 800 MHz CPU
  • Two SFP+ ports (1 Gigabit Ethernet, 10 Gigabit Ethernet, Aurora)
  • RJ45 (1 GbE) [2]
  • Clock reference 
  • PPS time reference
  • External RX, TX LO input ports [3]
  • Built-in GPSDO 
  • 1 Type A USB host port 
  • 1 micro-USB port (serial console, JTAG) 
  • Trusted Platform Module v1.2 [4]
  • Watchdog timer
  • OpenEmbedded Linux
  • USRP Hardware Driver™ (UHD) open-source software API version 3.11.0 or later
  • RF Network on Chip (RFNoC™) FPGA development framework
  • Xilinx Vivado 2017.4 Design Suite (license not included)
  • GNU Radio support maintained by Ettus Research™ through GR-UHD, an interface to UHD distributed by GNU Radio

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