{"id":136,"date":"2017-12-28T10:05:41","date_gmt":"2017-12-28T10:05:41","guid":{"rendered":"http:\/\/tenettech.net\/SDR\/product\/import-placeholder-for-127\/"},"modified":"2026-04-20T23:11:25","modified_gmt":"2026-04-20T23:11:25","slug":"usrp-x310","status":"publish","type":"product","link":"http:\/\/tenettech.net\/SDR\/product\/usrp-x310\/","title":{"rendered":"USRP X310"},"content":{"rendered":"

The Ettus Research USRP X310 is a high-performance, scalable software defined radio (SDR) platform for designing and deploying next generation wireless communications systems. The hardware architecture combines two extended-bandwidth daughterboard slots covering DC \u2013 6 GHz with up to 120 MHz of baseband bandwidth, multiple high-speed interface options (PCIe, dual 10 GigE, dual 1 GigE), and a large user-programmable Kintex-7 FPGA in a convenient desktop or rack-mountable half-wide 1U form factor. In addition to providing best-in-class hardware performance, the open source software architecture of X310 provides cross-platform UHD driver support making it compatible with a large number of supported development frameworks, reference architectures, and open source projects.\u00a0\u00a0<\/em><\/p>\n\n\n\n\n\n
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Operating Systems<\/strong><\/p>\n<\/td>\n

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Linux<\/p>\n

Windows<\/p>\n<\/td>\n<\/tr>\n

\n

Development Frameworks<\/strong><\/p>\n<\/td>\n

\n

GNU Radio<\/a><\/p>\n

Xilinx Vivado 2015.2 Design Suite<\/a><\/p>\n<\/td>\n<\/tr>\n

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Turn-Key Applications<\/strong><\/p>\n<\/td>\n

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Amarisoft LTE 100<\/a><\/p>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Table 1: Operating systems, development frameworks, and reference applications<\/p>\n

High-Performance User-Programmable FPGA<\/strong><\/p>\n

At the heart of the USRP X310, the XC7K410T FPGA provides high-speed connectivity between all major components within the device including radio frontends, host interfaces, and DDR3 memory.\u00a0 The default FPGA core provided with UHD provides all of the functional blocks for digital down-conversion and up-conversion, fine-frequency tuning, and other DSP functions allowing it to be interchangeable with other USRP devices using the UHD architecture.\u00a0 The large Kintex-7 FPGA provides additional space for developers to incorporate custom DSP blocks and is compatible with a large number of USRP supported development frameworks, reference architectures, and open source projects.<\/p>\n

\n\n\n\n\n\n\n\n\n\n
<\/td>\nUSRP N210<\/strong><\/td>\nUSRP X300<\/strong><\/td>\nUSRP X310<\/strong><\/td>\n<\/tr>\n
FPGA<\/strong><\/td>\nSpartan3\u00a0XC3SD3400A<\/td>\nKintex 7-325T<\/td>\nKintex 7 -410T<\/td>\n<\/tr>\n
Logic Cells<\/strong><\/td>\n53k<\/td>\n328k<\/td>\n406k<\/td>\n<\/tr>\n
Memory<\/strong><\/td>\n2,268 Kb<\/td>\n16,020 Kb<\/td>\n28,620 Kb<\/td>\n<\/tr>\n
Multipliers<\/strong><\/td>\n126<\/td>\n840<\/td>\n1540<\/td>\n<\/tr>\n
Clock Rate<\/strong><\/td>\n100 MHz<\/td>\n200 MHz<\/td>\n200 MHz<\/td>\n<\/tr>\n
Streaming Bandwidth per Channel (16-bit)
\n<\/strong><\/td>\n		25 MS\/s<\/td>\n200 MS\/s<\/td>\n200 MS\/s<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/div>\n

Table 2: FPGA resource comparison<\/p>\n

Multiple High-Speed Interface Options<\/strong><\/p>\n

The USRP X310 provides multiple interface options.\u00a0 Out of the box, 1 GigE provides a convenient way to get started. For extended bandwidth and lower latency applications such as PHY\/MAC research, PCIe x4 provides an efficient bus for deterministic operation. Applications using network recorders or multiple processing nodes can be best served by the 10 GigE interface option.<\/p>\n

Additional Features- GPSDO, GPIO, 1 GB DDR3, Synchronization<\/strong><\/p>\n

The X310 includes many additional features that facilitate wireless system development.\u00a0 On-board 1GB DDR3 with flexible access through the FPGA reference design supplements the FPGA resources with buffering and data storage memory.\u00a0\u00a0An\u00a0optional internal GPSDO<\/a>\u00a0provides a high-accuracy frequency reference, and global timing alignment to within 50 ns when synchronized to the GPS system.\u00a0 The external GPIO connector allows users to control external components such as amplifiers and switches, accept inputs like event triggers, and observe debug signals. \u00a0The USRP X310 also includes an internal JTAG adapter that allows FPGA developers to easily load and debug new FPGA images.<\/p>\n


\nProduct Photos<\/strong><\/p>\n

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\"USRP<\/p>\n

USRP X310 Rear View<\/p>\n

\"USRP<\/p>\n

USRP X310 Front Panel<\/p>\n

\"USRP<\/p>\n

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USRP X310 Rear Panel<\/p>\n

\"Dual<\/p>\n

Dual USRP X300\/X310 in Rackmount (1U)<\/p>\n

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Features<\/strong>:<\/p>\n